In some integrated circuit memory devices, different operating modes can be selected on the semiconductor chip before packaging. For example, a memory device may be capable of operating in various modes, such as page mode, nibble mode, burst mode, and static mode. In such a memory device, the desired operation mode may be chosen by cutting a predetermined fuse or set of fuses. In addition, fuses can be used to select among other options relating to, for example, propagation delay adjustment, pulse width adjustment, transistor width adjustment, and current level adjustment. Fuses can also be used to repair memory devices, including defective memory cells. Thus, broadly stated, a semiconductor device can be programmed to exhibit a certain set of characteristics or features by selectively cutting or leaving intact various fuse elements. To determine the status of a particular fuse, a fuse signature circuit can be used to determine if the fuse element is cut or intact.
The aforementioned applications for fuses are described, for example, in U.S. Pat. No. 4,446,534 entitled "PROGRAMMABLE FUSE CIRCUIT," U.S. Pat. No. 4,730,129 entitled "INTEGRATED CIRCUIT HAVING FUSE CIRCUIT," U.S. Pat. No. 4,773,046 entitled "SEMICONDUCTOR DEVICE HAVING FUSE CIRCUIT AND DETECTING CIRCUIT FOR DETECTING STATES OF FUSES IN THE FUSE CIRCUIT," U.S. Pat. No. 5,428,311 entitled "FUSE CIRCUITRY TO CONTROL THE PROPAGATION DELAY OF AN IC," U.S. Pat. No. 5,491,444 entitled "FUSE CIRCUIT WITH FEEDBACK DISCONNECT," U.S. Pat. No. 5,701,274 entitled "SEMICONDUCTOR DEVICE WITH SELECTABLE DEVICE INFORMATION," U.S. Pat. No. 5,726,585 entitled "SWITCHING CIRCUIT FOR USE INA SEMICONDUCTOR MEMORYDEVICE," U.S. Pat. No. 5,767,732 entitled "CIRCUIT FOR PERMANENTLY ADJUSTING A CIRCUIT ELEMENT VALUE IN A SEMICONDUCTOR INTEGRATED CIRCUIT USING FUSE ELEMENTS," and U.S. Pat. No. 5,818,285 entitled "FUSE SIGNATURE CIRCUITS FOR MICROELECTRONIC DEVICES."
In addition to these applications, fuse elements or fuse circuits have also been used to perform selection functions. With reference to FIG. 1, a conventional semiconductor device 10 is shown to comprise a selection circuit 15 and an internal circuit 20. The selection circuit 15 typically has at least one fuse element (not shown), and controls the operation of the internal circuit 20 in accordance with a fuse cutting operation.
A circuit diagram of the selection circuit 15 according to the prior art is shown in FIG. 2. The selection circuit 15 includes a master fuse MF, which is electrically connected between a power supply voltage VCC and an output terminal ND1, and a resistor R1, which is electrically connected between the output terminal ND1 and a ground or common voltage VSS. The master fuse MF typically comprises a laser fuse. Before the master fuse MF is cut, the output terminal ND 1 is driven to a logically high level (hereinafter logic one level) that is approximately equal to the power supply voltage VCC, which thereby activates the internal circuit 20. Conversely, after the master fuse MF is cut, the output terminal ND1 is pulled down to a logically low level (hereinafter logic zero level) that is approximately equal to the ground or common voltage VSS, which thereby deactivates the internal circuit 20.
If the master fuse MF is cut imperfectly, however, the operation of the internal circuit 20 and ultimately the semiconductor device 10 may not be reliably predicted. For example, after the master fuse MF is cut, remnants of the master fuse MF may act as a resistor. This may cause the voltage level at the output terminal NDI to fall between the standard logic one and logic zero voltage levels, which can cause the behavior of the internal circuit 20 to be indeterminate.
Consequently, there exists a need for improved integrated circuit devices that can be reliably programmed through the use of fuses.